Streamlined NTRU Prime on FPGA

Abstract We present a novel full hardware implementation of Streamlined NTRU Prime, with two variants: high-speed, high-area and slower, low-area implementation. introduce several new techniques that improve performance, including batch inversion for key generation, high-speed schoolbook polynomial multiplier, an NTT multiplier combined CRT map, DSP-free modular reduction method, radix sorting module, encoders decoders. With the design, we achieve to-date fastest speeds 5007, 10,989, 64,026 cycles encapsulation, decapsulation, respectively, while running at 285 MHz on Xilinx Zynq Ultrascale+. The entire design uses 40,060 LUT, 26,384 flip-flops, 36.5 Bram, 31 DSP.